1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device and a manufacturing method thereof. In particular, this non-volatile semiconductor memory device is extremely useful to be embedded on a same semiconductor substrate with logic circuits which function is typically represented by a microcomputer.
2. Description of the Related Art
Semiconductor devices of upgraded performance can be developed by embedding non-volatile semiconductor memory cells in logic semiconductor devices on a silicon substrate. They have been widely utilized as embedded microcomputers for industrial machines, home electric appliances, on-vehicle equipment, etc. Generally, programs required for the microcomputers are stored in embedded non-volatile memories and optionally read out for use.
The cell structure of the non-volatile memory suitable for embedding within the logic semiconductor device described above includes a split gate type memory cell comprising a select MOS transistor and a memory MOS transistor. This is suitable for embedded use because of the following: Since a source side injection (SSI) with satisfactory injection efficiency can be adopted in this structure, the programming speed can be increased and the power supply area can be reduced. In addition, since memory cell select transistors and transistors connected therewith can be composed of low voltage transistors with small occupied areas, the area for the peripheral circuit can be reduced. Literatures relevant to those include, for example, JP-A Nos. 5-48113 (hereinafter referred to as Patent Document 1) and 5-121700 (hereinafter referred to as Patent Document 2), IEEE, Symposium on VLST Technology, Proceedings, pp 71 to 72, (hereinafter referred to as Non-Patent Document 1) and IEEE, 1997, Symposium on VLSI Technology, Proceedings, pp 63 to 64 (hereinafter referred to as Non-Patent Document 2).
The charge retention of the memory MOS transistor includes a floating gate type in which charges are stored in electrically isolated conductive polysilicon (Patent document 2, Non-Patent Document 1) and an MONOS type in which charges are stored in a dielectric film having a property of trapping charges such as a silicon nitride film (Patent document 1, and Non-Patent Document 2). The floating gate has been widely used for a program storing flash memory in mobile phones or a data storing large capacity flash memory and shows good charge retention characteristics. However, along with device scaling, it has become difficult to ensure a capacitive coupling ratio necessary for the potential control of the floating gate and the structure has been complicated. To suppress the leakage of the retained charges, an oxide film that surrounds the floating gate needs to have a thickness of about 8 nm or more, approaching the limit of device scaling intended for high speed operation and high integration. The charge retention is deteriorated extremely when even only one defect is present as a leakage path in an oxide film on the periphery of the floating gate.
On the other hand, the MONOS is generally poor compared with the floating gate in view of the charge retention characteristics, and the threshold voltage approaches a lower value as the logarithm of the time. Accordingly, while the MONOS has been known through the ages, it has yet been put to practical use only for some products. However, since this is a discrete trapping memory of storing charges in dielectrics, several leak paths, if any, do not lead to loss of entire retention charges and this is resistant to oxide film defects. Accordingly, this system has advantageous features that it is suitable for device scaling since even a thin oxide film of 8 nm or less can be used, the reliability is easily predictable since the retention is not lowered extremely due to defects with low probability, and the memory structure is simple to be embedded easily in logic circuits. With such view points, the MONOS has been again attracted attention in recent years along with the device scaling.
A split gate structure particularly suitable for device scaling includes a structure of forming one of MOS transistors with a side wall by self-alignment (Patent Document 1, Non-Patent Document 2). In this case, since an alignment margin in photolithography is not necessary and the gate length of a transistor formed by self-alignment can be less than the minimum resolution size of photolithography, a finer memory cell compared with the existent structure of forming each of the two transistors by a photomask can be attained.
Among the split gate type memory cells utilizing the self-alignment, the memory cell with self-align MONOS structure is suitable for embedding within a high speed logic circuit area, which is shown in the Patent-Document 3 and Non-Patent Document 2. FIG. 1 shows a typical cross sectional view of this memory cell. A memory gate 11 and a select gate 12 are formed above a semiconductor substrate 60. In the illustrated structure, the memory gate 11 is formed of an ONO film comprising a SiO2 film 13, an Si3N4 film 14, and an SiO2 film 15 (hereinafter the multi-layered film thus formed is referred to as an ONO film) and a polysilicon electrode of the side wall structure on the side wall of a select gate 12. A cobalt silicide layer 16 is formed above diffusion areas 1, 5, the select gate 12, and the memory gate 11.
In the memory cell described above, since the select gate 12 is formed previously in view of the structure, the select gate 12 and a gate oxide film of a logic circuit area formed simultaneously therewith can be formed in a state where the quality of the silicon substrate interface is good. Since a transistor having a thin film gate at a high speed operation and sensitive to interface quality can be formed previously, the performance of the logic circuit area and the select gate transistor is improved. Since the stored information can be read only by the operation of the transistor with high performance select gate transistor and all of transistors connected therewith can be constituted with a thin film low voltage transistors, reading speed can be increased and the circuit area can be reduced. In FIG. 1, only the memory area in the semiconductor memory device is illustrated and the logic circuit area is not shown.
The manufacturing process of a split gate MONOS memory cell has a feature of well matching with the standard CMOS process and it is suitable for a microcomputer or the like in which a non-volatile memory is embedded. This is to be described referring to an example of a manufacturing step for a memory area together with a logic circuit area together in a semiconductor memory device, in conjunction with difficulties involved therein. FIGS. 2 to 10 show production process flows in parallel with the CMOS logic process. In each of the figures, the left-hand part shows the cross section of a memory area and the right-hand part shows a cross section of a logic area to form CMOS. FIG. 2 shows a step of forming a gate dielectric film 6 and a gate electrode material 34 comprising polysilicon above a silicon substrate 60. The gate dielectric film 6 is used in common with the select transistor of the MONOS memory area and a transistor of a logic area. While not illustrated, a device isolation structure is formed using a usual method as a pre-stage in the manufacturing step for specific products. Successively, a gate electrode structure 12 of the memory area is formed by photolithography and dry etching (FIG. 3). Successively, an ONO film 18 comprising a SiO2 film 13, Si3N4 film 14, and a SiO2 film 15 is deposited (FIG. 4). Further, doped amorphous silicon is deposited as a second electrode material for forming a memory gate electrode material. Then, the amorphous silicon film is etched back by dry etching to leave an amorphous silicon film as side walls 11, 40 only on the side wall of the gate electrode (FIG. 5). From the side walls 11, 40 thus formed, one unnecessary side 40 of the memory gate is removed by dry etching and, further, the ONO film in the lower layer after removal of the side wall electrode is also removed. Further, impurity-doped areas 1, 5 with low concentration are formed (FIG. 6).
Then, as shown in FIG. 7, a gate electrode structure 17 in the logic area is formed by using photolithography and dry etching. From this state, a SiO2 film 19 is deposited as the side wall for both of the transistors in the MONOS memory cell and the logic area and then etched back. Then, a heavily doped region 18 with high concentration is formed (FIG. 8). To lower the resistance of the gate electrodes 12, 17 and the diffusion region 18, silicidation 27 is applied with cobalt (FIG. 9). Then, a first layer dielectric film 42 is deposited (FIG. 10) and planarization and contact area formation are performed. Subsequently, a standard process of metallization for about 3- to 6-layers is applied, but the description therefore is to be omitted.
In the self-align split gate type MONOS memory explained in the order of the manufacturing steps described above, the height of the memory gate electrode 11 is lower compared with the select gate electrode 16 in view of the structure forming the memory gate electrode 11 with the side wall. This produces a problem with the device scaling in the production rule.
FIG. 11 is a cross sectional view for explaining manufacturing process according to the 150-nm rule as the related art. FIG. 11 shows a main portion in FIG. 1 in which identical portions carry the same reference numerals. In accordance with the 150-nm rule, the height of the select gate electrode 12 is about 250 nm. On the other hand, the memory gate electrode 11 to be formed is slanted at the upper surface due to the side all structure. Accordingly, the lowest portion above the channel is from 200 nm to 150 nm. On the other hand, FIG. 12 shows a cross section in a case of manufacture according to the 90-nm rule. FIG. 12 also shows identical portions as those in FIG. 11. As illustrated in the drawing, the height of the select gate electrode 12 is reduced to about 150 nm. Accordingly, the height of the memory gate electrode 11 can be ensured only by about 100 nm to 50 nm at the lowest portion above the channel.
In a case where the height of the memory gate electrode 11 is not sufficient, implanted ions 49 can not be completely blocked by the gate electrode 11 as a mask upon ion implantation 49 for forming the diffusion region on the side of the channel by self-alignment, and the ions are implanted into the channel to cause a problem with the fluctuation of the threshold voltage. As a specific example, it is considered such a case in which the gate electrode 11 comprises polysilicon and phosphorous are implanted under the implantation condition under 40 keV and at 1×1013 atoms/cm2 as ion implantation for the diffusion region. Among a plurality times of the ion implantation steps, the most penetrating condition is extracted. When the projected range Rp of the ion implantation and the standard deviation σ (ΔRp) are trial-calculated, they are: σ=60 nm and σ=25 nm respectively (the values are approximated in the case of amorphous silicon). The distance necessary for decreasing the amount of implanted ions to such a level as giving no effects on the threshold voltage of the channel is about 135 nm (Rp+3×σ=135 nm). That is, this means that at least 135 nm height is necessary for the upper end of the gate electrode. In a case of the 150-nm rule shown in FIG. 11, since the height of the memory gate electrode is from 200 nm to 150 nm, there is no problem. On the other hand, in a case of the device scaling to the 90-nm rule shown in FIG. 20, since the height of the memory gate electrode is only about 100 nm to 50 nm and it is lower than 135 nm described above, a problem arises with penetration of the implanted ions into the channel portion. Curves 80 in FIGS. 11 and 12 are curves showing the distribution of the implanted ions 49 in the direction of the depth. There are shown a projected range Rp of the implantation ions, the standard deviation σ thereof, and the concentration Conc. In the example of FIG. 11, since the height of the memory gate electrode is higher than the projected range 3σ of the implanted ions, the problem does not arise with penetration of the implanted ions to the channel area. On the other hand, in the example of FIG. 12, since the height of the gate electrode is lower than the projected range 3σ of the implanted ions, a problem arises with penetration of the implanted ions to the channel area. This is shown by reference 50 in the drawing.
It is conceivable that countermeasures for the penetration of the implanted ions simply include (1) a method of increasing the height of the gate electrode and (2) a method of decreasing the energy for implantation. However, in the method (1) described above, the thickness of the photoresist film is reduced for the change of a KrF light source to the ArF light source, or for higher accuracy also in the KrF light source. Accordingly, the removing amount is restricted in the dry etching using the photoresist film as a mask, which makes it difficult to further increase the film thickness for the gate electrode material. Also in the method (2) described above, the ion implantation condition is determined in view of the requirement for countermeasure of the short circuit failure between the diffusion region-substrate upon silicidation. Accordingly, such change is difficult so long as necessary silicide is applied irrespective of the scaling.